The present invention relates to the photolithography process on a semiconductor wafer in the process of manufacturing semiconductor devices and more particularly to the process of fabricating the gate electrodes of CMOS type devices on a semiconductor wafer. The critical dimension (CD) of the gate width determines the speed of the device. The width of the gate determines the speed. The width is in the direction between the source and the drain as illustrated by width “w” in FIG. 1. The shorter or narrower the width “w” of the gate the faster the device is. If the gate width is too short there is too much heat and if the width is too wide the device is too slow. It is desirable that the width of all of the gates for all of the devices on a given wafer be uniform to have the same characteristics. It is therefore desirable that the critical dimension (CD) of the gate be the same across the whole wafer. However, this critical dimension (CD) without compensation changes randomly or systematically as a function of locations on the wafer. This change is known to be caused by etching, CMP polishing, and film deposition variations.
The current process of manufacturing gate electrodes on semiconductor devices includes providing a wafer with a layer of polysilicon on the wafer, generating a photomask for the areas to provide gates, coating the wafer with photoresist, transmitting light using a scanner with a lens (reducing image 4 times for example) across the wafer to expose the photoresist with light except in the areas of the mask, developing the exposed areas of the photoresist by a wet etch to leave on the gate areas unexposed by the photoresist, dry etching the exposed areas to dry etch all the polysilicon away except the gate area under the remaining unexposed photoresist and then removing the photoresist to leave the polysilicon gates. The scanner is a camera such as a Nikon S305 that scans one die on the wafer at a time. The camera remains fixed and a table holding the wafer is moved to scan the light onto the wafer die by die. For an example, a desired gate width “w” is 0.12 micrometer. This may be achieved using a photoresist known as PAR 707 of Sumitomo and a light dosage of 20 millijoules per square cm.
As discussed above this critical dimension (CD) width changes across the wafer under prior art processing. The current process attempts to solve this problem by exposing a test wafer from a batch to a given dosage (20 millijoules per square cm for example). Measurements are then taken across the wafer by a Scattered Electron Machine (SEM). There are some zones where the gates may be over exposed and too narrow such as say 0.10 μm, some zones that are under exposed and 0.14 μm and some that are just right. The conventional method of solving this across the wafer critical dimension (CD) variation is what is termed bi-shot exposure (BSE). The bi-shot exposure (BSE) is a process wherein, after the measurement in the SEM, the exposure tool defines and provides different dose for each location to compensate for CD variation caused by the error sources discussed above such as topography or subsequent etch process as discussed above. It has been determined that this BSE exposure process does not correct the problem and sometimes the BSE process makes for more error.